The process flow for semiconductor fabrication of integrated circuits (ICs) may include front-end-of-line (FEOL), middle-end-of-line (MEOL), and back-end-of-line (BEOL) processes. The FEOL process may include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MEOL process may include gate contact formation. The BEOL processes may include a series of wafer processing steps for interconnecting the semiconductor devices created during the FEOL and MEOL processes. Successful fabrication and qualification of modern semiconductor chip products involves an interplay between the materials and the processes employed. In particular, the formation of conductive material plating for passive on glass (POG) devices in BEOL processes is an increasingly challenging part of the process flow.